The rapid developments in nanoelectronics has increasingly required more rapidly acting transistors, especially metal oxide field effect transistors (MOSFETs). A performance increase is generally obtained by the reduction of transistor dimensions.
This however can be expensive and difficult to achieve since the key technologies of chip production, like the lithographic process and the etching process must be replaced by systems which are more powerful. An alternative technique is the use of materials which are more capable of higher performance. The materials which are available for this purpose are especially strained silicon, strained silicon-germanium alloys (Si—Ge) or silicon-carbon (Si—C) and silicon-germanium-carbon (Si—Ge—C). The use of silicon or Si—Ge, Si—C or Si—Ge—C in a certain elastic strain state, improves the material characteristics, especially the preeminently important carrier mobility of the electrons and holes for electronic components. The use of these and other high quality materials enables a significant performance increase of Si based high power electronic components like MOSFETs and MODFETs without the need to reduce the critical structural sizes of the electronic components.
Such elastically strained layer systems require epitaxial growth on special substrates or stress relaxed layers, so-called “virtual substrates” whose production with low defect densities is very expensive and difficult (F. Schaeffler, Semiconductor Sci. and Tech. 12 (1997), pages 1515-1549).
Up to now the production of nanocrystalline layers with currently available substrate materials has been greatly limited or the quality of the layers has been poor. Different crystal structures as well as different lattice parameters between the substrate and the layer material (lattice mismatch) generally limited the monocrystalline growth of layers of higher quality. When monocrystalline layers are deposited with unmatched lattice parameters, these tend to grow first with mechanical stresses, that is their lattice structures differ in this state from the original. Should the deposited layer exceed a critical layer thickness, the mechanical stresses break down with defect formation and the lattice structure comes closer to the original. This process is termed stress relation and is referred to below as “relaxation”.
With layer thicknesses which are required for electronic components, through this relaxation, dislocations are incorporated at the interface between the formed layer and the substrate while in a detrimental manner, many dislocations run from the interface to the layer surface (so-called threading dislocations). Since most of these dislocations travel through newly grown layers, they significantly cause deterioration of the electrical and optical properties of the material. By the terms “dislocation density” or also “defect density”, such threading dislocation densities are intended.
Since the silicon germanium (Si—Ge) material system is thermodynamically a fully miscible system, the compounds can be formed with optional concentrations. Silicon and germanium are characterized indeed by the same crystallographic structure but differ with respect to the lattice parameters by about 4.2%, that is an Si—Ge-layer or a pure Ge layer can grow in a strained state on silicon. Carbon can be substitutionally incorporated into silicon only to about 2 atomic percent to reduce the lattice parameters.
Within the state of the art for the production for example of strained silicon on for example stress free qualitatively high-grade silicon-germanium alloy layers on a silicon substrate, there is the use of the so-called “graded layer” upon which in a further step the desired strained layer can be deposited. The “graded layer” can be a silicon-germanium layer whose germanium concentration increases toward the surface until the desired germanium content is achieved in a continuous or stepwise manner. Since to maintain the layer quality only an increase in the germanium content of bout 10 atom % per μm is required, such layers are up to 10 micrometer thick to achieve the current Ge concentration. The layer growth of this “graded layer” is described by E. A. Fitzgerald et al, Thin Solid Films, 294 (1997) 3-10.
This method leads disadvantageously to high layer roughnesses, to dislocation multiplication with an extremely nonhomogeneous distribution of threading dislocations and thus to a crystallographic tipping of regions so that an expensive polishing of the layers is required before strained silicon can be formed on the thus made buffer in an additional epitaxy step. Because of the extremely nonhomogeneous distribution of the threading dislocations, in spite of the comparatively reduced dislocation density, locally regions with a higher dislocation density are formed at which the transistor function is very negatively effected. Before the second layer deposition, usually in a CVD reactor or in a molecular beam epitaxy apparatus, a special wafer cleaning must be carried out to ensure monocrystalline growth and to minimize the incorporation of impurities or undesired doping substances. The many drawbacks, large layer thicknesses, long growth duration, expensive polishing, cleaning and the two or more epitaxial steps that are required, reduces the output of the wafers and makes this process expensive, limits the quality and in general makes the method uneconomical. Because of the large layer thicknesses of the graded layers of several micrometers of Si—Ge, these also have a substantially poorer thermal conductivity which can give rise to a so-called “self-heating” of the electronic component so that their use in electronic components has been highly unsatisfactory.
For these reasons method of producing ultra thin stress relaxed layers of higher quality are of considerable interest.
From WO 99/38201, a method is known that permits the production of thin stress relaxed Si—Ge buffer layers. Nevertheless it is a drawback of this method that also here a plurality of expensive technological steps are required so that no ultra thin “virtual substrate” can be produced. After the epitaxial deposition of the layer to be relaxed, an ion implantation is carried out which is followed by a heat treatment, a surface cleaning and an epitaxial depositing anew.